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vishay siliconix SIC769CD document number: 64981 s09-1181-rev. b, 29-jun-09 www.vishay.com 1 new product integrated drmos power stage description the SIC769CD is an integrated solution that contains pwm optimized n-channel mosfets (high side and low side) and a full featured mosfet driver ic. the device complies with the intel drmos standard for desktop and server v core power stages. the SIC769CD delivers up to 35 a continuous output current and operates from an input voltage range of 3 v to 16 v. the integrated mosfets are optimized for output voltages in the ranges of 0.8 v to 2.0 v with a nominal input voltage of 12 v. the device can also deliver very high power at 5 v output for asic applications. the SIC769CD incorporates an advanced mosfet gate driver ic. this ic accepts a single pwm input from the v r controller and converts it into the high side and low side mosfet gate drive signals. the driver ic is designed to implement the skip mode (smod) function for light load efficiency improvement. adaptive dead time control also works to improve efficiency at all load points. the SIC769CD has a thermal warning (thdn) that alerts the system of excessive junction temperature. the driver ic includes an enable pin, uvlo and shoot through protection. the SIC769CD is optimized for high frequency buck applications. operating frequencies in excess of 1 mhz can easily be achieved. the SIC769CD is packaged in vishay siliconix high performance powerpak mlp6 x 6 package. compact co-packaging of components helps to reduce stray inductance, and hence increases efficiency. features ? integrated gen iii mosfets and drmos compliant gate driver ic ? enables v core switching at 1 mhz ? easily achieve > 90 % efficiency in multi-phase, low output voltage solutions ? low ringing on the vswh pin reduces emi ? pin compatible with drmos 6 x 6 version 3.0 ? tri-state pwm input function prevents negative output voltage swing ? 5 v logic levels on pwm ? mosfet threshold voltage optimized for 5 v driver bias supply ? automatic skip mode operation (smod) for light load efficiency ? under-voltage lockout ? built-in bootstrap schottky diode ? adaptive deadtime and shoot through protection ? thermal shutdown warning flag ? low profile, thermally enhanced powerpak ? mlp 6 x 6 40 pin package applications ? cpu and gpu core voltage regulation ? server, computer, workstat ion, game console, graphics boards, pc SIC769CD application diagramm figure 1 5 v controller gate dri v er ic 12 v to load v out p g n d gl c g n d v s w boot v i n gh v dr v v ci n smod dsbl# p w m thd n SIC769CD 2 1 39 40 3 8 nnw r 3 6 8 to 14 p2 nnw q phase 4 15, 29 to 35, p3 7 5, 37, p1 36 16 to 2 8
www.vishay.com 2 document number: 64981 s09-1181-rev. b, 29-jun-09 vishay siliconix SIC769CD new product note: a. t a = 25 c and all voltages referenced to p gnd = c gnd unless otherwise noted. stresses beyond those listed under "absol ute maximum ratings" may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other condi tions beyond those indicated in the operational sections of t he specifications is not implied. exposure to absolute maximum rating/condi tions for extended periods may affect device reliability. note: a. recommended operating conditions are s pecified over the entire temperature range, and all voltages referenced to p gnd = c gnd unless otherwise noted. ordering information part number package SIC769CD-t1-e3 powerpak mlp66-40 sic769db reference board absolute maximum ratings t a = 25 c, unless otherwise noted parameter symbol min. max. unit input voltage v in - 0.3 20 v switch node voltage (dc) v sw - 0.3 20 switch node voltage gnd - 8 v (< 20 ns, 10 j) 30 (< 100 ns) drive input voltage v drv - 0.3 7.0 control input voltage v cin - 0.3 7.0 logic pins v pwm , v dsbl# , v thdn , v smod - 0.3 v cin + 0.3 boot voltage dc (referenced to c gnd ) v bs - 0.3 27 boot voltage < 200 ns transient (referenced to c gnd ) - 0.3 29 boot to phase voltage dc v bs_ph - 0.3 7 boot to phase voltage < 200 ns - 0.3 9 ambient temperature range t a - 40 125 maximum junction temperature t j 150 c storage junction temperature t stg - 65 150 soldering peak temperature 260 recommended operating conditions parameter symbol min. typ. max. unit input voltage v in 3.0 12 16 v control input voltage v cin 4.5 5.5 drive input voltage v drv 4.5 5.5 switch node v sw_dc 12 16 thermal resistance ratings parameter symbol typ. max. unit maximum power dissipation p d tbd w high side junction to pcb (pin 11) pcb = 250 mm x 250 mm; no forced airflow r thjpcbhs 9 c/w low side junction to pcb (pin 30) pcb = 250 mm x 250 mm; no forced airflow r thjpcbls 3
document number: 64981 s09-1181-rev. b, 29-jun-09 www.vishay.com 3 vishay siliconix SIC769CD new product notes: a. typical limits are establ ished by characterization and are not production tested. b. guaranteed by design. electrical specifications parameter symbol test conditions unless specified v dsbl# = v smod = 5 v, v in = 12 v, v vdrv = v vcin 5 v, t a = 25 c min. typ. a max. unit power supplies v cin control input current i vcin v dsbl# = 0 v, no switching 20 a v dsbl# = 5 v, no switching 400 v dsbl# = 5 v, f s = 300 khz, d = 0.1 600 drive input current (dynamic) i vdrv f s = 300 khz, d = 0.1 11 16 ma f s = 1000 khz, d = 0.1 40 54 bootstrap supply bootstrap switch forward voltage v bs diode v vcin = 5 v, forward bias current 2 ma 0.60 0.75 v control inputs (pwm, dsbl#, smod) pwm rising threshold v th_pwm_r 3.5 3.8 4.2 v pwm falling threshold v th_pwm_f 0.8 1.0 1.2 pwm tristate rising threshold v th_tri_r 0.9 1.3 1.8 pwm tristate falling threshold v th_tri_f 3.4 3.7 4.0 pwm tristate rising th reshold hysteresis v hys_tri_r 200 mv pwm tristate falling threshold hysteresis v hys_tri_f 300 tristate hold-off time b t tsho 150 ns pwm input current i pwm v pwm = 5 v 250 a v pwm = 0 v - 250 smod, dsbl# logic input voltage v logic_lh rising (low to high) 2.0 v v logic_lh falling (high to low) 0.8 pull down impedance r thdn 5 k resistor pull-up to v cin 40 thdn output low v thdnl 0.04 v protection thermal warning flag set 150 c thermal warning flag clear 135 thermal warning flag hysteresis 15 under voltage lockout v uvlo rising, on threshold 3.3 3.9 v under voltage lockout falling, off threshold 2.5 2.9 under voltage lockout hysteresis v uvlo_hyst 400 mv high side gate discharge resistor b r hs_dscrg v vdrv = v vcin = 0 v; v in = 12 v 20.2 k
www.vishay.com 4 document number: 64981 s09-1181-rev. b, 29-jun-09 vishay siliconix SIC769CD new product note: a. typical mosfet parameters are provided as a design guide. note: a. min. and max. are not 100 % production tested. mosfet specifications parameter symbol test conditions unless specified v vcin = v dsbl# = 5 v, v vin = 12 v, t a = 25 c min. typ. a max. unit high side v ds v gs = 0 v, i ds = 250 a 20 v r ds(on)_h v gh = 5 v, resistance measured at package pins 6.0 m low side v ds v gs = 0 v, i ds = 250 a 20 v r ds(on)_l v gl = 5 v, resistance measured at package pins 1.7 m timing specifications parameter symbol test conditions unless specified v vdrv = v vcin = v dsbl# = 5 v, v vin = 12 v, t a = 25 c min. typ. max. unit turn off propagation delay high side a t d_on_hs 25 % of pwm to 90 % of gh 10 20 30 ns rise time high side t r_hs 10 % to 90 % of gh 8 fall time high side t f_hs 90 % to 10 % of gh 8 turn off propagation delay low side a t d_off_ls 75 % of pwm to 90 % of gl 10 20 30 rise time low side t r_ls 10 % to 90 % of gl 8 fall time low side t f_ls 90 % to 10 % of gl 8 dead time rising t dead_on 10 % of gl to 10 % of gh 15 dead time falling t dead_off 10 % of gh to 10 % of gl 15
document number: 64981 s09-1181-rev. b, 29-jun-09 www.vishay.com 5 vishay siliconix SIC769CD new product timing definitions note: gh is referenced to the high side source. gl is referenced to the low side source. SIC769CD block diagram region definition symbol 1 turn off propagation delay ls t d_off_ls 2 fall time ls t f_ls 3 dead time rising t dead_on 4rise time hst r_hs 5 turn off propagation delay hs t d_off_hs 6fall time hst f_hs 7 dead time falling t dead_off 8 rise time ls t r_ls p w m gh gl s w 1234 56 7 8 10 % 90 % 10 % 90 % 75 % 25 % figure 2 u v lo v dr v gh gl c g n d p g n d v s w h boot v i n v ci n p w m dsbl# thd n smod thermal w arning tristate p w m ast c n tl dcm detect phase
www.vishay.com 6 document number: 64981 s09-1181-rev. b, 29-jun-09 vishay siliconix SIC769CD new product detailed operational description pwm input with tr istate function the pwm input receives the pw m control signal from the v r controller ic. the pwm input is designed to be compatible with standard controllers using two state logic (h and l) and advanced controllers that incor porate tristate logic (h, l and tristate) on the pwm output. for two state logic, the pwm input operates as follows. when pwm is driven above v th_pwm_r the low side is turned off and the high side is turned on. when pwm input is driven below v th_pwm_f the high side turns off and the low side turns on. for tristate logic, the pwm input operates as abov e for driving the mosfets. however, there is an third state that is entered into as the pwm output of tristate compatible controller enters its high impedance state during shut-down. the high impedance state of the controller's pwm output allows the SIC769CD to pull the pwm input into the tristate region (see the tristate voltage threshold diagram below). if the pwm input stays in this region for the tris tate hold-off period, t tsho , both high side and low side mosfets are turned off. this function allows the v r phase to be disabled without negative output voltage swing caused by inductor ringing and saves a schottky diode clamp. the pwm and tristate regions are separated by hysteresis to prevent false triggering. the SIC769CD incorporates pwm voltage thresholds that are compatible with 5 v logic. the sic769acd incorporates logic thresholds that are compatible with 3.3 v logic. disable (dsbl#) in the low state, the dsbl# pin shuts down the driver ic and disables both high-side and lo w-side mosfet. in this state, the standby current is minimized. if dsbl# is left unconnected an internal pull-down resistor will pull the pin down to c gnd and shut down the ic. diode emulation mode (smod) skip mode when smod pin is low the diode emulation mode is enabled. this is a non-synchronous c onversion mode that improves light load efficiency by reduci ng switching losses. conducted losses that occur in synchro nous buck regulators when inductor current is negative are also reduced. circuitry in the gate drive ic detects the when inductor current crosses zero and automatically stops switching the low side mosfet. see smod operation diagram for additional details. this function can be also be used for a pre-biased output voltage. if smod is left unconnected, an internal pull up resistor will pull the pin up to v cin (logic high) to disable the smod function. thermal shutdown warning (thdn) the thdn pin is an open drain si gnal that flags the presence of excessive junction temperature. connect a maximum of 20 k to pull this pin up to v cin . an internal temperature sensor detects the junction temperature. the temperature threshold is 150 c. when this junction temperature is exceeded the thdn flag is set. when the junction temperature drops below 135 c the device will clear the thdn signal. the SIC769CD does not stop operation when the flag is set. the decision to shutdown must be made by an external thermal control function. voltage input (v in ) this is the power input to the drain of the high-side power mosfet. this pin is connected to the high power intermediate bus rail. switch node (v swh and phase) the switch node v swh is the circuit pwm regulated output. this is the output applied to the filter circuit to deliver the regulated high output for the buck converter. the phase pin is internally connected to the switch node v swh . this pin is to be used exclusively as the return pin for the boot capacitor. a 20.2 k resistor is connected between gh and phase to provide a discharge path for the hs mosfet in the event that v cin goes to zero while v in is still applied. ground connections (c gnd and p gnd ) p gnd (power ground) should be externally connected to c gnd (control signal ground). the layout of the printed circuit board should be such that the inductance separating the c gnd and p gnd should be a minimum. transient differences due to inductance effects between these two pins should not exceed 0.5 v. control and drive supp ly voltage input (v drv ,v cin ) v cin is the bias supply for the gate drive control ic. v drv is the bias supply for the gate drivers. it is recommended to separate these pins through a resistor. this creates a low pass filtering effect to avoid coupling of high frequency gate drive noise into the ic. bootstrap circuit (boot) the internal bootstrap switch and an external bootstrap capacitor form a charge pump that supplies voltage to the boot pin. an integrated bootst rap diode is incorporated so that only an external capacitor is necessary to complete the bootstrap circuit. connect a boot strap capacitor with one leg tied to boot pin and th e other tied to phase pin. shoot-through protection and adaptive dead time (ast) the SIC769CD has an internal adaptive logic to avoid shoot through and optimize dead time. the shoot through protection ensures that bot h high-side and low-side mosfet are not turned on the same time. the adaptive dead time control operates as follows. when pwm input goes high the ls gate starts to go low after a few ns. when this signal crosses through 1.7 v the logic to switch the hs gate on is activated. when pwm goes low the hs gate goes low. when the hs gate-to-source drive signal crosses through 1.7 v the logic to turn on the ls gate is activated. this feature helps to adjust dead time as gate transitions change with respect to output current and temperature. under voltage lockout (uvlo) during the start up cycle, the uv lo disables t he gate drive holding high-side and low-side mosfet gate low until the input voltage rail has reached a point at which the logic circuitry can be safely activated. the SIC769CD also incorporates logic to clamp the gate drive signals to zero when the uvlo falling edge triggers the shutdown of the device. as an added precaution, a 20.2 k resistor is connected between gh and phase to provide a discharge path for the hs mosfet.
vishay siliconix SIC769CD document number: 64981 s09-1181-rev. b, 29-jun-09 www.vishay.com 7 new product tristate pwm voltage threshold diagram smod operation diagram device truth table dsbl# smod pwm gh gl open xxl l l xxl l h lllh (i l > 0), l (i l 0) h lhhl h hhhl h hllh figure 3 v th_tri_f v th_p w m_r v th_tri_r v th_p w m_f p w m gh gl t tsho t tsho figure 4 dsbl smod p w m gh gl v s w i l > 0 i l = 0 t d(o n ) t d(off)
www.vishay.com 8 document number: 64981 s09-1181-rev. b, 29-jun-09 vishay siliconix SIC769CD new product pin configuration figure 5 - powerpak mlp 6 x 6 40p pin out - top view v i n p2 a g n d p1 v s w h p3 30 v s w h 29 v s w h 2 8 p g n d 27 p g n d 26 p g n d 25 p g n d 24 p g n d 23 p g n d 22 p g n d 21 p g n d 40 p w m 39 disbl# 3 8 thd n 37 c g n d 36 gl 35 v s w h 34 v s w h 33 v s w h 32 v s w h 31 v s w h smod 1 v ci n 2 v dr v 3 boot 4 c g n d 5 gh 6 phase 7 v i n 8 v i n 9 v i n 10 20 p g n d 19 p g n d 1 8 p g n d 17 p g n d 16 p g n d 15 v s w h 14 v i n 13 v i n 12 v i n 11 v i n pin description pin number symbol description 1 smod disable low side gate operation. active low. 2v cin this will be the bias supply input for control ic (5 v). 3v drv ic bias supply and gate drive supply voltage (5 v). 4 boot high side driver bootstrap voltage pin for external bootstrap capacitor. 5, 37, pad1 c gnd control signal ground. it should be connected to p gnd externally. all pins internally connected. 6 gh gate signal output pin for high side mosfet. pin for monitoring. 7 phase return pin for the hs bootstrap capacitor. connect a 0.1 f ceramic capacitor from this pin to the boot pin (4). 8 to 14, pad2 v in input voltage for power stage. it is the drain of the high-side mosfet. 15, 29 to 35, pa d 3 vswh it is the phase node between high side mosfet source and low side mosfet drain. it should be connected to an output inductor. all pi ns internally connected. 16 to 28 p gnd power ground. 36 gl gate signal output pin for low side mosfet. pin for monitoring. 38 thdn thermal shutdown open drain output. use a 10k pull up resistor to v cin . 39 dsbl# disable pin. active low. 40 pwm pwm input logic signal. compatib le with tristate controller function.
vishay siliconix SIC769CD document number: 64981 s09-1181-rev. b, 29-jun-09 www.vishay.com 9 new product electrical characteristics i cin (ma) vs. temperature at frequency = 300 khz d = 10 %, v cin = v drv = 5 v pwm falling threshold (v) vs. temperature (c) v cin = v drv = 5 v dsbl falling threshold (v) vs. temperature (c) v cin = v drv = 5 v 0.0 0.2 0.4 0.6 0. 8 1.0 - 40 - 25 - 10 5 20 35 50 65 8 095110125140 temperat u re (c) i ci n (ma) - 40 - 25 - 10 5 20 35 50 65 8 0 95 110 125 140 temperat u re (c) p w m t sh ( v ) 0. 8 0.9 1.0 1.1 1.2 1.3 - 40 - 25 - 10 5 20 35 50 65 8 0 95 110 125 140 temperat u re (c) dsbl t sh ( v ) 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 i drv (ma) vs. temperature at frequency = 300 khz d = 10 %, v cin = v drv = 5 v pwm rising threshold (v) vs. temperature (c) v cin = v drv = 5 v dsbl rising threshold (v) vs. temperature (c) v cin = v drv = 5 v - 40 - 25 - 10 5 20 35 50 65 8 0 95 110 125 140 temperat u re (c) i dr v (ma) 6 8 10 12 14 16 1 8 20 - 40 - 25 - 10 5 20 35 50 65 8 0 95 110 125 140 temperat u re (c) p w m t sh ( v ) 3.0 3.2 3.4 3.6 3. 8 4.0 4.2 4.4 - 40 - 25 - 10 5 20 35 50 65 8 0 95 110 125 140 temperat u re (c) dsbl t sh ( v ) 1.45 1.50 1.55 1.60 1.65 1.70 1.75 1. 8 0 1.40
www.vishay.com 10 document number: 64981 s09-1181-rev. b, 29-jun-09 vishay siliconix SIC769CD new product electrical characteristics smod falling threshold (v) vs. temperature (c) v cin = v drv = 5 v i cin + i drv (ma) vs. temperature at frequency = 1 mhz d = 10 %, v cin = v drv = 5 v pwm falling tristate (v) vs. temperature (c) v cin = v drv = 5 v - 40 - 25 - 10 5 20 35 50 65 8 0 95 110 125 140 temperat u re (c) smod t sh ( v ) 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 - 40 - 25 - 10 5 20 35 50 65 8 0 95 110 125 140 temperat u re (c) i ci n (ma) 0 10 20 30 40 50 60 - 40 - 25 - 10 5 20 35 50 65 8 0 95 110 125 140 temperat u re (c) p w m t sh ( v ) 1.0 1.1 1.2 1.3 1.4 1.5 1.6 smod rising threshold (v) vs. temperature (c) v cin = v drv = 5 v i drv (ma) vs. temperature at frequency = 1 mhz d = 10 %, v cin = v drv = 5 v pwm rising tristate threshold (v) vs. temperature (c) v cin = v drv = 5 v - 40 - 25 - 10 5 20 35 50 65 8 0 95 110 125 140 temperat u re (c) smod t sh ( v ) 1.40 1.45 1.50 1.55 1.60 1.65 1.70 1.75 1. 8 0 - 40 - 25 - 10 5 20 35 50 65 8 0 95 110 125 140 temperat u re (c) i dr v (ma) 25 30 35 40 45 50 - 40 - 25 - 10 5 20 35 50 65 8 0 95 110 125 140 temperat u re (c) p w m t sh ( v ) 3.0 3.2 3.4 3.6 3. 8 4.0 4.2 4.4
vishay siliconix SIC769CD document number: 64981 s09-1181-rev. b, 29-jun-09 www.vishay.com 11 new product electrical characteristics dsbl falling threshold vs. v cin smod falling threshold vs. v cin pwm falling threshold vs. v cin v ci n ( v ) dsbl t sh ( v ) 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 4.7 4. 8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 5.6 v ci n ( v ) dsbl t sh ( v ) 4.7 4. 8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 5.6 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 v ci n ( v ) p w m t sh ( v ) 4.7 4. 8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 5.6 0.90 0.95 1.00 1.05 1.10 1.15 dsbl rising threshold vs. v cin smod rising threshold vs. v cin pwm rising threshold vs. v cin v ci n ( v ) dsbl t sh ( v ) 4.7 4. 8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 5.6 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 v ci n ( v ) smod t sh ( v ) 4.7 4. 8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 5.6 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 v ci n ( v ) p w m t sh ( v ) 4.7 4. 8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 5.6 3.0 3.2 3.4 3.6 3. 8 4.0 4.2 4.4
www.vishay.com 12 document number: 64981 s09-1181-rev. b, 29-jun-09 vishay siliconix SIC769CD new product electrical characteristics startup at v in = 12 v, v out = 1.2 v, f s = 1 mhz, i out = 30 a disable smod at v in = 12 v, v out = 1.2 v, f s = 1 mhz driver performance at v in = 12 v, v out = 1.2 v, f s = 1 mhz, i out = 10 a v in v out v cin lind smod v sw v sw gh gl pwm power off at v in = 12 v, v out = 1.2 v, f s = 1 mhz, i out = 30 a enable smod at v in = 12 v, v out = 1.2 v, f s = 1 mhz driver performance at v in = 12 v, v out = 1.2 v, f s = 1 mhz, i out = 10 a v in v out v cin lind smod v sw v sw gh gl pwm
vishay siliconix SIC769CD document number: 64981 s09-1181-rev. b, 29-jun-09 www.vishay.com 13 new product typical power loss in SIC769CD powerpak mlp66-40 package typical efficiency curves figure 6 - SIC769CD powerpak mlp66-40 package package dissipation ( w ) i out (a) 0 1 2 3 4 5 6 7 8 9 0 5 10 15 20 25 30 35 40 1 mhz 300 khz v i n = 12 v , v out = 1.2 v , v dr v = v ci n = 5 v ; n o air flo w ihlp5050ez-01 ind u ctor: 1 mhz = 220 nh; 300 khz = 470 nh p loss_pkg = p v ci n + p v dr v + p v i n - p out_ v s w figure 7 efficiency ( % ) i out (a) v i n = 12 v , v out = 1.2 v , v dr v = v ci n = 5 v ; n o air flo w ihlp5050ez-01 ind u ctor: 1 mhz = 220 nh, 0. 8 m ; 500 khz = 330 nh, 1.1 m ; 300 khz = 470 nh, 1.3 m efficiency % = 100 x p v out /(p v ci n + p v dr v + p v i n ) 70 75 8 0 8 5 90 95 0 5 10 15 20 25 30 35 40 300 khz 500 khz 1 mhz
www.vishay.com 14 document number: 64981 s09-1181-rev. b, 29-jun-09 vishay siliconix SIC769CD new product package dimensions notes: 1. use millimeters as th e primary measurement. 2. dimensioning and tolerances conform to asme y14.5m-1994. 3. n is the number of terminals. nd is the number of terminals in x-direction and ne is the number of terminals in y-direction . 4. dimension b applies to plated terminal and is m easured between 0.20 mm and 0.25 mm from terminal tip. 5. the pin #1 identifier must be existed on the top surface of t he package by using indentation ma rk or other feature of package body . 6. exact shape and size of this feature is optional. 7. package warpage max. 0.08 mm. 8. applied only for terminals. dim millimeters inches min. nom. max. min. nom. max. a (8) 0.70 0.75 0.80 0.027 0.029 0.031 a1 0.00 - 0.05 0.000 - 0.002 a2 0.20 ref. 0.008 ref. b (4) 0.20 0.25 0.30 0.078 0.098 0.011 d 6.00 bsc 0.236 bsc e 0.50 bsc 0.019 bsc e 6.00 bsc 0.236 bsc l 0.35 0.40 0.45 0.013 0.015 0.017 n (3) 40 40 nd (3) 10 10 ne (3) 10 10 d2-1 1.45 1.50 1.55 0.057 0.059 0.061 d2-2 1.45 1.50 1.55 0.057 0.059 0.061 d2-3 2.35 2.40 2.45 0.095 0.094 0.096 e2-1 4.35 4.40 4.45 0.171 0.173 0.175 e2-2 1.95 2.00 2.05 0.076 0.078 0.080 e2-3 1.95 2.00 2.05 0.076 0.078 0.080 k1 0.73 bsc 0.028 bsc k2 0.21 bsc 0.008 bsc figure 8 - powerpak mlp 66-40 40 1 2 x 2 x pin 1 dot b y marking mlp66-40 (6 mm x 6 mm) 10 11 20 21 30 31 56 4 top v ie w bottom v ie w side v ie w a b c d 0.10 c b e 0.10 c a a 0.0 8 c a1 a2 0.41 k2 k1 d2-1 pin #1 dent e2-1 e d2-3 d2-2 e2-3 e2-2 ( n d-1)x e ref. ( n d-1)x e ref. 0.10 m c a b
vishay siliconix SIC769CD document number: 64981 s09-1181-rev. b, 29-jun-09 www.vishay.com 15 new product land pattern dimensions tape and reel carrier tape dimensions notes: 1. 10 sprocket hole pitch cumulative tolerance 0.2. 2. camber in compliance with eia 481. 3. pocket position relative to sprocket hole measured as true position of pocket, not pocket hole. vishay siliconix maintains worldwide manufacturing capability. pr oducts may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?64981 . figure 9 - powerpak mlp 66-40 1 1 0.025 0.100 0.100 0.100 0.100 0.025 40 0.100 0.100 0.100 0.100 0.100 0.100 0.600 2.600 1.700 0.320 0.310 40 2.200 2.200 0.276 0.276 0.200 4.600 figure 10 - powerpak mlp 66-40 12.00 1.75 0.1 0.25 0.30 0.05 b o section a-a a o = 6.30 b o = 6.30 k o = 1.10 ? 1.5 + 0.1 - 0.0 a o k o r 0.3 max. ? 1.50 min. r 0.25 2.00 0.10 see note 3 4.00 see note 1 a a 16.0 0.3 7.5 0.1 see note 3
document number: 91000 www.vishay.com revision: 18-jul-08 1 disclaimer legal disclaimer notice vishay all product specifications and data are subject to change without notice. vishay intertechnology, inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, ?vishay?), disclaim any and all liability fo r any errors, inaccuracies or incompleteness contained herein or in any other disclosure relating to any product. vishay disclaims any and all li ability arising out of the use or application of any product describ ed herein or of any information provided herein to the maximum extent permit ted by law. the product specifications do not expand or otherwise modify vishay?s terms and conditions of purcha se, including but not limited to the warranty expressed therein, which apply to these products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of vishay. the products shown herein are not designed for use in medi cal, life-saving, or life-sustaining applications unless otherwise expressly indicated. customers using or selling vishay products not expressly indicated for use in such applications do so entirely at their own risk and agree to fully indemnify vishay for any damages arising or resulting from such use or sale. please contact authorized vishay personnel to obtain written terms and conditions regarding products designed for such applications. product names and markings noted herein may be trademarks of their respective owners.

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